By Franz, Rubinoff, Morris (Editors) Alt

ISBN-10: 0120121077

ISBN-13: 9780120121076

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IN-350 Планирование и внедрение LDAP - download pdf or read online

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4 Iterative Array Switching Circuits Highly parallel networks [31] have been investigated from the point of view of switching theory. Much of this work has been directed toward 38 HIGHLY PARALLEL INFORMATION PROCESSING SYSTEMS development of techniques for the analysis and synthesis of networks that realize a particular mapping of primary two-dimensional input patterns to primary output patterns. Only limited results have been obtained in developing synthesis methods. Similarly, only limited results have been obtained in the analysis of stability of networks.

And each module contains 226 bits of storage for switching and a 69-bit instruction/data word. About 400 logic elements are also used. Comments. This approach seems well beyond practical hardware limits until appropriate bit storage can be provided at a realistic cost. However, the Michigan studies have demonstrated that the improved path building capabilities give a definite advantage both in programming and operating efficiency. For example, for the matrix inversion process noted for the Holland machine, the minimum possible program length to invert an M x M matrix is 3M 1, as compared to the 3Mz for the planar array.

Paths are formed through communication logic in the storage module. The operand in the T module is gated down the path to the P module and from there to the A box. A somewhat different and more flexible path building procedure than in Holland’s machine is used. Also, a richer instruction repertoire is made available since the instruction execution need only be mechanized in A boxes. The instruction word is 36 bits including the instruction code and path building data which are equivalent to the operand address.

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Advances in Computers, Vol. 7 by Franz, Rubinoff, Morris (Editors) Alt


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